Integrated circuit performing authentication using challenge-response protocol and method of using the integrated circuit
US11368319B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 9, 2020 |
| Grant date | Jun 21, 2022 |
| Priority date | — |
| Expiry date | Dec 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/12
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to an integrated circuit and a method of using the integrated circuit used to perform authentication using a challenge-response method. The challenge-response method includes an internal challenge generator, a physically unclonable function (PUF) block, and a response generator. The internal challenge generator is configured to receive a challenge, generate a plurality of internal challenges corresponding to the challenge, and generate at least one valid internal challenge among the plurality of internal challenges using screen information. The physically unclonable function (PUF) block is configured to generate a plurality of valid internal responses respectively changing according to the plurality of valid internal challenges. The response generator is configured to output a response generated using the plurality of valid internal responses.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.