Patent · US Active

Simultaneous low quiescent current and high performance LDO using single input stage and multiple output stages

US11372436B2 · kind B2 · utility

3Cited by
54References
5Claims
0Family size

Assignee

Inventor

Key dates

Filing dateOct 14, 2019
Grant dateJun 28, 2022
Priority date—
Expiry dateDec 26, 2039

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG05F1/59
  • WIPO fieldControl
  • WIPO sectorInstruments

Abstract

A simultaneous low quiescent current and high performance low dropout (LDO) voltage regulator is disclosed. In some implementations, the LDO voltage regulator includes a first and a second pass transistors configured to receive an input voltage (Vin). The LDO voltage regulator further includes an error amplifying module having a first output, a second output, a first input, and a second input. The error amplifying module can further include a first output stage configured to drive the gate of the first pass transistor during a high performance (HP) mode, and a second output stage configured to drive the gate of the second pass transistor during the HP mode and during a low power (LP) mode.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.