Extra-resilient cache for resilient storage array
US11372557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 20, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Nov 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/314
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data storage array is configured for m-way resiliency across a first plurality of storage nodes. The m-way resiliency causes the data storage array to direct each top-level write to at least m storage nodes within the first plurality, for committing data to a corresponding capacity region allocated on each storage node to which each write operation is directed. Based on the data storage array being configured for m-way resiliency, an extra-resilient cache is allocated across a second plurality of storage nodes comprising at least s storage nodes (where s>m), including allocating a corresponding cache region on each of the second plurality for use by the extra-resilient cache. Based on determining that a particular top-level write has not been acknowledged by at least n of the first plurality of storage nodes (where n m), the particular top-level write is redirected to the extra-resilient cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.