Dynamic reconfigurable multi-level cache for multi-purpose and heterogeneous computing architectures
US11372758B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Jun 18, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/601
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments of a system for dynamic reconfiguration of cache are disclosed. Accordingly, the system includes a plurality of processors and a plurality of memory modules executed by the plurality of processors. The system also includes a dynamic reconfigurable cache comprising of a multi-level cache implementing a combination of an L1 cache, an L2 cache, and an L3 cache. The one or more of the L1 cache, the L2 cache, and the L3 cache are dynamically reconfigurable to one or more sizes based at least in part on an application data size associated with an application being executed by the plurality of processors. In an embodiment, the system includes a reconfiguration control and distribution module configured to perform dynamic reconfiguration of the dynamic reconfigurable cache based on the application data size.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.