Programmable chip enable for switching and selecting functions to reduce data loading and increase throughput
US11372781B2 · kind B2 · utility
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6References
20Claims
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Key dates
| Filing date | Aug 26, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Dec 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/40
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes arrays of memory devices each having a data bus coupled to the data bus of a host memory channel by means of a switching tree. The switching tree is a tree of multiplexers that are controlled to couple the data lines of a single array to the data bus. In some embodiments, a first portion of the chip enable (CE) lines of a memory module are used to enable arrays of memory devices and a second portion are used to control the switching tree. The first portion may control a switching tree coupling the first portion to the enable inputs of the arrays.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.