Patent · US Active

Generic physical layer providing a unified architecture for interfacing with an external memory device and methods of interfacing with an external memory device

US11373694B1 · kind B1 · utility

0Cited by

3References

13Claims

0Family size

Assignee

SKYECHIP SDN BHD · MY

Inventors

Soon Chieh Lim · Merang, MY
Chee Hak Teh · Kampung Bukit Kechil, MY
Tat Hin Tan · Bayan Lepas, MY

Key dates

Filing date	Feb 6, 2021
Grant date	Jun 28, 2022
Priority date	—
Expiry date	Feb 6, 2041

Classification

Technology area (CPC G)Physics
CPC primaryG11C8/06
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A generic physical layer providing a unified architecture for interfacing with an external memory device. The physical layer comprises a transmit data path for transmitting a parallel data to the external memory device and a receive data path for receiving a serial data from the external memory device. The generic physical layer is characterized by a receive enable logic for masking strobe of the serial data, wherein the transmit data path and the receive data path each comprising a FIFO circuit, a data rotator and an adjustable-delay logic for delay tuning and a per-bit-deskew for multi-lane support.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.