Semiconductor structure and method for forming the same
US11373912B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 17, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Jul 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor structure includes forming a dielectric layer on a substrate, including a first region and a second region; forming a first gate opening and a second gate opening in dielectric layer of the first region and the second region, respectively; forming initial work function layers on bottom and sidewall surfaces of the first gate opening and the second gate opening; and performing at least one cycle of a combined etching process to etch the initial work function layers formed in the first gate opening and form a work function layer in the second gate opening from the initial work function layers. Each cycle of the combined etching process includes performing an oxide etching process to etch the initial work function layers; and then performing a main etching process on the initial work function layers to remove an exposed initial work function layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.