Flash with shallow trench in channel region and method for manufacturing the same
US11374014B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 21, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Aug 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/68
Abstract
The present invention discloses a flash. A channel region comprises a first shallow trench formed in the surface area of a semiconductor substrate. A tunneling dielectric layer and a polysilicon floating gate are formed in the first shallow trench and extended to the outside of the first shallow trench. A control dielectric layer and a polysilicon control gate are sequentially formed on the two side surfaces in the width direction and the top surface of the polysilicon floating gate. A source region and a drain region are formed in a self-aligned manner in active regions on the two sides in the length direction of the polysilicon floating gate. The present invention further discloses a method for manufacturing a flash. The present invention can break through the limitation of the length of the channel on the size of the memory cell, thus reducing the area of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.