Array substrate having protection region on same layer as gate insulating layer and manufacturing method thereof
US11374038B2 · kind B2 · utility
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4Claims
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Key dates
| Filing date | Apr 15, 2019 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Jan 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate and a manufacturing method thereof, wherein the array substrate includes a substrate; an active layer disposed on the substrate; a gate insulating layer disposed on the active layer; a gate disposed on the gate insulating layer; and a protection region dispose between the active layer and the gate, wherein the protection region is disposed on two sides of the gate and disposed on a same layer as the gate insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.