Methods of reducing capacitance in field-effect transistors
US11374104B2 · kind B2 · utility
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20References
20Claims
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Key dates
| Filing date | Sep 30, 2019 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Dec 12, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76224
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a fin protruding from a substrate, a first and a second metal gate stacks disposed over the fin, and a dielectric feature defining a sidewall of each of the first and the second metal gate stacks. Furthermore, the dielectric feature includes a two-layer structure, where sidewalls of the first layer are defined by the second layer, and where the first and the second layers have different compositions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.