Cascode amplifier bias circuits
US11374540B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Aug 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2200/78
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Bias circuits and methods for silicon-based amplifier architectures that are tolerant of supply and bias voltage variations, bias current variations, and transistor stack height, and compensate for poor output resistance characteristics. Embodiments include power amplifiers and low-noise amplifiers that utilize a cascode reference circuit to bias the final stages of a cascode amplifier under the control of a closed loop bias control circuit. The closed loop bias control circuit ensures that the current in the cascode reference circuit is approximately equal to a selected multiple of a known current value by adjusting the gate bias voltage to the final stage of the cascode amplifier. The final current through the cascode amplifier is a multiple of the current in the cascode reference circuit, based on a device scaling factor representing the relative sizes of the transistor devices in the cascode amplifier and in the cascode reference circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.