Method for controlling semiconductor device
US11374563B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 4, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Sep 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/23
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes first and second electrodes, a semiconductor part therebetween and first to third control electrodes between the first electrode and the semiconductor part. The semiconductor part includes first and third layers of a first-conductivity-type and second and fourth layers of a second-conductivity-type. The second, third and fourth layers are provided between the first layer and the first electrode, between the second layer and the first electrode, and between the first layer and the second electrode, respectively. To the first to third control electrodes, first to third voltages greater than the threshold voltage thereof are applied at first to third timings, respectively. The third, second and first voltages are reduced to a lower level than the threshold voltage at a fourth timing after the first to third timings, at a fifth timing after the fourth timing and at a sixth timing after the fifth timing, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.