Self-diagnostic counter
US11374576B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Dec 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K23/58
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In described examples, a counter system includes a counter, a parity detector, a toggle flop, and a comparator. The counter iterates a count through a set of binary states in response to a clock signal, so that a binary value of a single bit of the count changes at each iteration. The parity detector detects the parity of the count. The toggle flop output is coupled to the toggle flop input. The toggle flop outputs a binary flop value. The binary flop value toggles between zero and one in response to the toggle flop input and the clock signal. The comparator compares the parity of the count and the toggle flop output, and outputs a first comparator value if the parity of the count and the toggle flop output are the same, and a second comparator value if the parity of the count and the toggle flop output are different.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.