Patent · US Active

Interleaving ADC error correction methods for Ethernet PHY

US11374601B2 · kind B2 · utility

2Cited by

8References

28Claims

0Family size

Assignee

TEXAS INSTRUMENTS INCORPORATED · US

Inventors

Raghu Ganesan · Bengaluru, IN
Saravanakkumar Radhakrishnan · Virudhunagar, IN
Kalpesh Laxmanbhai RAJAI · Bengaluru, IN
Soumyajit Roul · Bengaluru, IN
Sumantra Seth · Bengaluru, IN

Key dates

Filing date	Mar 12, 2021
Grant date	Jun 28, 2022
Priority date	—
Expiry date	Mar 12, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH04B2001/1063
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

A receiver circuit includes an interleaved ADC, a first delay circuit, a second delay circuit, a first processing channel, a second processing channel, and an interleaving ADC timing error detector circuit. The interleaved ADC includes a first ADC and a second ADC in parallel. The first delay circuit delays a first clock signal provided to the first ADC. The second delay circuit delays a second clock signal provided to the second ADC. The first processing channel processes data samples provided by the first ADC, and includes a first slicer. The second processing channel processes data samples provided by the second ADC, and includes a second slicer. The interleaving ADC timing error detector circuit controls delay of the first delay circuit and the second delay circuit based on an output signal of the first slicer, and an output signal or an input signal of the second slicer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.