Mapping bit positions using predicted error values
US11374704B2 · kind B2 · utility
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14Claims
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Key dates
| Filing date | May 7, 2020 |
| Grant date | Jun 28, 2022 |
| Priority date | — |
| Expiry date | Jun 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L1/0071
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Aspects described herein include a method comprising predicting, based on one or more transmission characteristics, error values for a sequence of bit positions used for modulating data within a packet. The method further comprises generating a bitmap that maps one or more payload bits and one or more padding bits of the packet to respective bit positions of the sequence. The one or more padding bits are preferentially mapped to respective bit positions having relatively greater error values. The method further comprises modulating the sequence according to the bitmap.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.