Methods and systems for single-event upset fault injection testing

US11378622B1 · kind B1 · utility

Assignee

• Raytheon Company · US

Inventors

• Patrick Fleming · Arlington, US
• Mustafa Amin · El Segundo, US
• James Bynes, III · El Segundo, US
• Patrick Llorens · El Segundo, US
• Dale D. Kachuche · El Segundo, US
• Brian A. Clebowicz · Manhattan Beach, US
• William Rowe · Middletown, US
• Alfredo Rene Lara · Norwalk, US
• Neal Pollack · El Segundo, US

Key dates

• Filing date: Jan 5, 2021
• Grant date: Jul 5, 2022
• Expiry date: Jan 5, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/2268
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

Fault injection testing for field programmable gate array (FPGA) devices including: interfacing with a FPGA device under test (DUT); imaging a configuration RAM (CRAM) of the FPGA DUT with a first configuration image to define a first operational function of the FPGA DUT where the CRAM includes a plurality of CRAM bits, injecting a plurality of single event upsets into a portion of the plurality of the CRAM bits while the FPGA DUT is operating; concurrently monitoring operations of the FPGA DUT and a reference FPGA device; comparing outputs of the FPGA DUT with outputs of the reference FPGA device during concurrent operations, and if there is a mismatch between the outputs of the FPGA DUT and the reference FPGA, determining that error events have occurred within the FPGA DUT; and storing the error events and CRAM location data associated with corresponding single event upsets in an error log.