Methods and apparatus for using load and store addresses to resolve memory dependencies
US11379242B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2017 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Jan 2, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4806
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may include elastic datapaths or pipelines, through which software threads or iterations of loops, may be executed. Throttling circuitry may be coupled along an elastic pipeline in the integrated circuit. The throttling circuitry may include dependency detection circuitry that dynamically detect memory dependency issues that may arise during runtime. To mitigate these dependency issues, the throttling circuitry may assert stall signals to upstream stages in the pipeline. Additionally, the throttling circuitry may control the pipeline to resolve a store operation prior to a corresponding load operation in order to avoid store/load conflicts. In an embodiment, the throttling circuitry may include a validator circuit, a rewind block, a revert block, and a flush block. The throttling circuitry may pass speculative iterations through the rewind block, and later validate the speculative iterations using the validator block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.