Verification method and system for operation result based on reconfigurable butterfly unit
US11379554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 10, 2021 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Mar 20, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present application discloses a verification system and method for an operation result based on a reconfigurable butterfly unit. The system is applicable to a digital signal processing (DSP) chip. The DSP chip includes a reconfigurable butterfly unit. The reconfigurable butterfly unit may be reconfigured into two modes: a first verification mode and a second verification mode. The system includes: a controller, a memory, a verification unit, a first data gating unit, and a second data gating unit. The technical solution in the present application is used to overcome the disadvantage that an existing verification system and an existing verification method consume large hardware resources, thereby reducing the implementation costs of operation result verification.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.