Architecture of in-memory computing memory device for use in artificial neuron
US11379714B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2019 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Feb 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An in-memory computing memory device is disclosed. The memory device comprises an array of memory cells, a plurality of word lines, a plurality of bit lines, (M+1) input circuits, a wordline driver and an evaluation circuitry. The array is divided into (M+1) lanes and each lane comprises P memory cell columns and an input circuit. The input circuit in each lane charges a predefined bit line with a default amount of charge proportional to an input synapse value and then distributes the default amount of charge to the other second bit lines with a predefined ratio based on a constant current. The evaluation circuitry couples a selected number of the bit lines to an accumulate line and convert an average voltage at the accumulate line into a digital value in response to a set of (M+1) input synapse values and the activated word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.