Chips and electronics devices
US11380368B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2019 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Dec 11, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed chip includes a storage module, pins, a control module, a first connection and a second connection. The storage module includes a first and a second storage array groups, which respectively include a plurality of first storage arrays and a plurality of second storage arrays. The pins are located on the side of the first storage array group away from the second storage array group. The control module is located between the first storage array group and the second storage array group. The first connection pin connects to the control module; and the second connection connects the control module to the first and the second storage array groups. The first connection line has a length less than the distance from the control module to the second storage array group at far side of the control module. The chip reduces the parasitic capacitance introduced by the first connection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.