Method of manufacturing integrated circuit device
US11380552B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 25, 2020 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Apr 25, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In order to manufacture an integrated circuit device, a feature layer is formed on a substrate in a first area for forming a plurality of chips and in a second area surrounding the first area. The feature layer has a step difference in the second area. On the feature layer, a hard mask structure including a plurality of hard mask layers stacked on each other is formed. In the first area and the second area, a protective layer covering the hard mask structure is formed. On the protective layer, a photoresist layer is formed. A photoresist pattern is formed by exposing and developing the photoresist layer in the first area by using the step difference in the second area as an alignment key.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.