Partial reverse concatenation for data storage devices using composite codes
US11381258B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 6, 2020 |
| Grant date | Jul 5, 2022 |
| Priority date | — |
| Expiry date | Feb 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2957
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a system includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to cause the processor to write, by the processor, data to a storage medium of a data storage system using a partial reverse concatenated modulation code. The partial reverse concatenated modulation code comprises encoding the data by applying a C2 encoding scheme prior to encoding the data by applying one or more modulation encoding schemes, followed by encoding the data by applying a C1 encoding scheme subsequent to the encoding of the data with the one or more modulation encoding schemes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.