Clock data recovery circuit
US11385677B2 · kind B2 · utility
1Cited by
3References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Sep 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0041
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A clock data recovery circuit includes a deglitch filter circuit and a timer circuit. The deglitch filter circuit is configured to remove pulses of less than a predetermined duration from a data signal to produce a deglitched data signal. The timer circuit is coupled to the deglitch filter, and is configured to compare a duration of a pulse of the deglitched data signal to a threshold duration, and identify the pulse as representing a logic one based on the duration of the pulse exceeding the threshold duration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.