Memory controller for non-interfering accesses to nonvolatile memory by different masters, and related systems and methods
US11385829B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 2019 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Mar 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1042
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device can include a plurality of processing sources; a multiplexer (MUX) configured to assign read requests from the processing sources to predetermined time division multiplexer (TDM) command slots. A memory controller can generate nonvolatile memory (NVM) command and address data from read requests received from the MUX during the TDM command slots assigned to the read requests on a unidirectional command-address bus. The address data can include at least a bank address. The device can also receive read data on a unidirectional parallel data bus in synchronism with rising and falling edges of a received data clock. The read data can be received in TDM read slots having a predetermined order. A demultiplexer can provide the read data of each TDM read slot to one of the processing sources based on the TDM read slot position in the predetermined order. Related methods and systems are also disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.