Secure firmware management with hierarchical boot sequence using last known good firmware
US11385902B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 15, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Feb 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system includes one or more memory devices, non-resettable memory elements and a processor. The first memory device is configured to store in the one or more memory devices (i) a first version of a multi-stage bootstrap program for bootstrapping the computer system, the bootstrap program including a self-test program that tests the bootstrap program, and (ii) a second version of the bootstrap program known to be trustworthy. The non-resettable memory elements are configured to store non-resettable indicators including at least a self-test-request indicator and a self-test-passed indicator. The processor is configured to retrieve the first version of the bootstrap program, and, if the first version is at least as recent as the trustworthy second version, to bootstrap the computer system securely using the first version and the non-resettable indicators.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.