Method and apparatus for error correction encoding compressed data
US11385962B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Nov 5, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Nov 15, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Designs of controllers for flash memory array are described. A controller is designed to form data packs of a predefined size with compressed data segments in different sizes. The data packs are encoded with ECC in two dimensions. When the data packs are read out, the ECC is applied in two dimensions to detect and correct errors that can be corrected by the ECC.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.