Security systems and methods for integrated circuits
US11386234B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2019 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Nov 3, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2221/032
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for verifying integrity of content of an integrated circuit's registers, the system being operative in conjunction with an integrated circuit including at least one memory, at least one processor, and a multiplicity of registers, the system comprising register content verification logic configured, when in a first mode aka “Study Mode”, to read at least some of the registers' content, to compute a first hash on the content, and to store the first hash thereby to provide an up-to-date reference hash, and, at least on occasion, when in a second mode aka “Verify Mode”, to compute at least one second hash on the content, to compare the second hash to the reference hash and, accordingly, to provide a content verification output (aka “fault detection” output) indicative of whether the reference and second hashes are equal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.