Techniques for simulation-based timing path labeling for multi-operating condition frequency prediction
US11386252B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 8, 2021 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Mar 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques improve integrated circuit design by employing multi-operating condition frequency prediction for statically timed designs through spice-based timing path labeling and statistical analysis. Design management component (DMC) can randomly determine and generate sample timing paths based on parameters of characteristics associated with the sample timing paths, the parameters determined based on random seed values; simulate responses of the sample timing paths; and generate vectorized data based on the simulated responses. DMC determines a trained model representing timing path properties and operating conditions of sample timing paths based on statistical analysis of vectorized data. Static timing analysis (STA) component can perform STA on design information of integrated circuitry design and determine an operating condition of a timing path of the design based on the STA. DMC can determine or predict another operating condition(s) associated with the design based on the operating condition and the trained model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.