Semiconductor circuit and semiconductor circuit layout system
US11386254B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 23, 2019 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Aug 5, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit and a layout system of the semiconductor circuit, the semiconductor circuit including a latch; a feedback inverter that receives an output signal of the latch via a first node and provides a feedback signal to the latch responsive to the output signal of the latch; and an output driver which receives the output signal of the latch via the first node and provides an output signal externally of the semiconductor circuit. The output driver includes an even number of inverters, and the latch, the feedback inverter, and the output driver share a single active region formed without isolation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.