Method and apparatus for built in redundancy analysis with dynamic fault reconfiguration
US11386973B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | May 18, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Oct 23, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/4402
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present embodiments provides a memory repair solution finding device and method which find a fault by testing a memory and find a repair solution in parallel and dynamically reconfigure the stored fault information to minimize a repair solution searching time with an optimal repair rate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.