Wafer level sequencing flow cell fabrication
US11387096B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 12, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Aug 12, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01N2021/058
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method for forming sequencing flow cells can include providing a semiconductor wafer covered with a dielectric layer, and forming a patterned layer on the dielectric layer. The patterned layer has a differential surface that includes alternating first surface regions and second surface regions. The method can also include attaching a cover wafer to the semiconductor wafer to form a composite wafer structure including a plurality of flow cells. The composite wafer structure can then be singulated to form a plurality of dies. Each die forms a sequencing flow cell. The sequencing flow cell can include a flow channel between a portion of the patterned layer and a portion of the cover wafer, an inlet, and an outlet. Further, the method can include functionalizing the sequencing flow cell to create differential surfaces.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.