Semiconductor device and method of manufacturing the same
US11387144B2 · kind B2 · utility
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37References
8Claims
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Key dates
| Filing date | Oct 14, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Oct 14, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are semiconductor devices and methods of manufacturing the same. The method comprises providing a layout comprising a first group that includes first and second patterns and a second group that includes third and fourth patterns, examining a bridge risk region in the layout, biasing one end of at least one of the first and third patterns, and forming first to fourth conductive patterns by respectively using the first to fourth patterns of the layout. The one end of at least one of the first and third patterns are adjacent to the bridge risk region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.