Semiconductor device
US11387229B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 23, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Jan 1, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed is a semiconductor device comprising a logic cell including first and second active regions spaced apart in a first direction on a substrate, first and second active patterns on the first and second active regions and extend in a second direction, first and second source/drain patterns on the first and second active patterns, gate electrodes extending in the first direction to run across the first and second active patterns and arranged in the second direction at a first pitch, first lines in a first interlayer dielectric layer on the gate electrodes and each electrically connected to the first source/drain pattern, the second source/drain pattern, or the gate electrode, and second lines in a second interlayer dielectric layer on the first interlayer dielectric layer and extending parallel to each other in the first direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.