Three-dimensional semiconductor devices and methods of fabricating the same
US11387253B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 24, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Jul 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/314
Abstract
A three-dimensional semiconductor device including a conductive layer disposed on a substrate and including a first conductivity-type impurity; an insulating base layer disposed on the conductive layer; a stack structure including a lower insulating film disposed on the insulating base layer, and a plurality of gate electrodes and a plurality of mold insulating layers alternately stacked on the lower insulating film, wherein the insulating base layer includes a high dielectric material; a vertical structure including a vertical channel layer penetrating through the stack structure and a vertical insulating layer disposed between the vertical channel layer and the plurality of gate electrodes, the vertical structure having an extended area extending in a width direction in the insulating base layer; and an isolation structure penetrating through the stack structure, the insulating base layer and the conductive layer, and extending in a direction parallel to an upper surface of the substrate, wherein the conductive layer has an extension portion extending along a surface of the vertical channel layer in the extended area of the vertical structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.