Array substrate with connection portion connecting power bus and power line and display panel
US11387310B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 14, 2019 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Mar 1, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An array substrate and a display panel are disclosed. The array substrate includes: a base substrate including a display region and a peripheral region; a plurality of sub-pixels in the display region; a plurality of data lines in the display region; a plurality of first power lines in the display region; a plurality of data lead lines in the peripheral region; a plurality of selection switches in the peripheral region; a plurality of data signal input lines in the peripheral region; a first power bus in the peripheral region; and a plurality of connection portions electrically connecting the first power bus to the plurality of first power lines, respectively. The plurality of connection portions include a plurality of first connection portions and a plurality of second connection portions on both sides of the plurality of first connection portions.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.