Trench gate depletion mode VDMOS device and method for manufacturing the same
US11387349B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2019 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Oct 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/513
Abstract
A trench gate depletion-type VDMOS device and a method for manufacturing the same are disclosed. The device comprises a drain region; a trench gate including a gate insulating layer on an inner wall of a trench and a gate electrode filled in the trench and surrounded by the gate insulating layer; a channel region located around the gate insulating layer; a well region located on both sides of the trench gate; a source regions located within the well region; a drift region located between the well region and the drain region; a second conductive-type doped region located between the channel region and the drain region; and a first conductive-type doped region located on both sides of the second conductive-type doped region and located between the drift region and the drain region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.