Half-bridge circuit with slew rate control
US11387735B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Jan 19, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2217/0081
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
First and second n-channel FETs are connected in series between first and second terminals with an intermediate switching node. First and second driver circuits drive gates of the first and second n-channel FETs, respectively, in response to drive signals. The first driver circuit does not implement slew-rate control. A first resistor and capacitor are connected in series between the output of the first driver circuit and an intermediate node. A first electronic switch is connected between the intermediate node and the first terminal. A second electronic switch is connected between the intermediate node and the gate terminal of the first n-channel FET. A second resistor and a third electronic switch are connected in series between the gate terminal of the first n-channel FET and the switching node. A control circuit generates the drive signals and a first, second and third control signal for the first, second and third electronic switch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.