Differential digital-to-time converter for even-order INL cancellation and supply noise/disturbance rejection
US11387833B1 · kind B1 · utility
9Cited by
14References
20Claims
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Key dates
| Filing date | Sep 3, 2021 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Sep 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/033
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method of quantization noise cancellation in a phase-locked loop (PLL) is provided according to certain aspects. The PLL includes a phase detector having a first input configured to receive a reference signal and a second input configured to receive a feedback signal. The method includes delaying the reference signal by a first time delay, delaying the feedback signal by a second time delay, receiving a delta-sigma modulator (DSM) error signal, and adjusting the first time delay and the second time delay in opposite directions based on the DSM error signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.