Content aware scheduling in a HEVC decoder operating on a multi-core processor platform
US11388405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 3, 2020 |
| Grant date | Jul 12, 2022 |
| Priority date | — |
| Expiry date | Nov 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N19/82
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method is provided for decoding an encoded video stream on a processor having a plurality of processing cores includes receiving and examining a video stream to identify any macroscopic constructs present therein that support parallel processing. Decoding of the video stream is divided into a plurality of decoding functions. The plurality of decoding functions is scheduled for decoding the video stream in a dynamic manner based on availability of any macroscopic constructs that have been identified and then based on a number of bytes used to encode each block into which each picture of the video stream is partitioned. Each of the decoding functions is dispatched to the plurality of processing cores in accordance with the scheduling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.