Memory device including interface circuit and method of operating the same
US11392324B2 · kind B2 · utility
1Cited by
10References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 24, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Sep 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M9/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.