Instructions for vector multiplication of signed words with rounding
US11392379B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2017 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Sep 27, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed embodiments relate to executing a vector multiplication instruction. In one example, a processor includes fetch circuitry to fetch the vector multiplication instruction having fields for an opcode, first and second source identifiers, and a destination identifier, decode circuitry to decode the fetched instruction, execution circuitry to, on each of a plurality of corresponding pairs of fixed-sized elements of the identified first and second sources, execute the decoded instruction to generate a double-sized product of each pair of fixed-sized elements, the double-sized product being represented by at least twice a number of bits of the fixed size, and generate a signed fixed-sized result by rounding the most significant fixed-sized portion of the double-sized product to fit into the identified destination.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.