Hardware-assisted paging mechanisms
US11392491B2 · kind B2 · utility
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3References
22Claims
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Key dates
| Filing date | Jun 27, 2018 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Jun 27, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7205
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processing circuitry for computer memory management includes memory reduction circuitry to implement a memory reduction technique; and reference count information collection circuitry to: access a memory region, the memory region subject to the memory reduction technique; obtain an indication of memory reduction of the memory region; calculate metrics based on the indication of memory reduction of cache lines associated with the memory region; and provide the metrics to a system software component for use in memory management mechanisms.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.