Aliased mode for cache controller

US11392498B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Abhijeet Ashok Chachad · Plano, US
• Timothy David Anderson · University Park, US
• Pramod Kumar Swami · Bengaluru, IN
• Naveen Bhoria · Plano, US
• David Matthew Thompson · Dallas, US
• Neelima Muralidharan · Sachse, US

Key dates

• Filing date: May 22, 2020
• Grant date: Jul 19, 2022
• Expiry date: May 22, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/608
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

An apparatus includes first CPU and second CPU cores, a L1 cache subsystem coupled to the first CPU core and comprising a L1 controller, and a L2 cache subsystem coupled to the L1 cache subsystem and to the second CPU core. The L2 cache subsystem includes a L2 memory and a L2 controller configured to operate in an aliased mode in response to a value in a memory map control register being asserted. In the aliased mode, the L2 controller receives a first request from the first CPU core directed to a virtual address in the L2 memory, receives a second request from the second CPU core directed to the virtual address in the L2 memory, directs the first request to a physical address A in the L2 memory, and directs the second request to a physical address B in the L2 memory.