Layout method of a semiconductor device and associated system
US11392747B2 · kind B2 · utility
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2References
20Claims
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Key dates
| Filing date | May 15, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | May 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A layout method of a semiconductor device is disposed. The layout method includes: disposing a first metal strip directed to a first clock signal and disposing a first block strip parallel with the first metal strip, wherein the first block strip is indicative of a first blockage which prevents a routing tool from placing another metal strip on the location of the first block strip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.