Shift register circuit, driving method thereof, gate driving circuit, and display apparatus
US11393384B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 13, 2018 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | May 26, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/08
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure is related to a shift register circuit. The shift register circuit may include a shift output circuit and N driving output circuits. N is an integer larger than 1. Among the N driving output circuits, an i-th driving output circuit may be respectively coupled to an i-th driving clock signal terminal of N driving clock signal terminals, a pull-up node of the shift output circuit, and an i-th driving output terminal of N driving output terminals. The i-th driving output circuit may be configured to input an i-th driving clock signal from the i-th driving clock signal terminal to the i-th driving output terminal under a control of the pull-up node, wherein i is a positive integer not greater than N.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.