Patent · US Active

Semiconductor device having a planar III-N semiconductor layer and fabrication method

US11393686B2 · kind B2 · utility

0Cited by

4References

5Claims

0Family size

Assignee

HEXAGEM AB · SE

Inventors

Jonas Ohlsson · Malmö, SE
Lars Samuelson · Malmö, SE
Kristian Storm · Hjärup, SE
Rafal Ciechonski · Lund, SE
Bart Markus · Hjärup, SE

Key dates

Filing date	Oct 5, 2018
Grant date	Jul 19, 2022
Priority date	—
Expiry date	Jan 6, 2039

Classification

Technology area (CPC H)Electricity
CPC primaryH10H20/817
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A semiconductor device having a planar III-N semiconductor layer, comprising a substrate comprising a wafer (101) and a buffer layer (102), of a buffer material different from a material of the wafer, the buffer layer having a growth surface (1021); an array of nano structures (1010) epitaxially grown from the growth surface; a continuous planar layer (1020) formed by coalescence of upper parts of the nano structures at an elevated temperature T, wherein the number of lattice cells spanning a center distance between adjacent nano structures are different at the growth surface and at the coalesced planar layer; a growth layer (1030), epitaxially grown on the planar layer (1020).

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.