Array apparatus and associated methods
US11393810B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2017 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Oct 22, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/69
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An apparatus including an array of field-effect transistors, each field-effect transistor including a channel, source and drain electrodes, and a gate electrode configured to enable the flow of electrical current to be varied, the gate electrode separated from the channel by a dielectric material configured to inhibit a flow of electrical current between the channel and gate electrode, wherein the gate electrode of each field-effect transistor is connected in parallel to the gate electrodes of the other field-effect transistors in the array, and wherein a respective two-terminal current-limiting component is coupled to each gate electrode such that, in the event that a defect in the dielectric material of a particular field-effect transistor allows a leakage current to flow between the channel and gate electrode of that field-effect transistor, the respective two-terminal current-limiting component limits the magnitude of the leakage current.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.