Vertical memory devices with reduced gate electrode coupling and methods of manufacturing the same
US11393841B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Jan 3, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
Abstract
Example embodiments disclose a vertical memory device and method of manufacturing the same. The device may include a plurality of gate electrodes and a plurality of insulation patterns and a channel that penetrates a first gate electrode and a first insulation pattern. The device may have a charge storage structure including a tunnel insulation pattern, a charge trapping pattern, and a blocking pattern that are sequentially stacked from an outer sidewall of a channel. The device may have a buried pattern structure that is surrounded by the tunnel insulation pattern and the charge trapping pattern. The charge trapping pattern may include a first vertically sloped portion having a first thickness in the horizontal direction and a second vertically sloped portion having a second thickness in the horizontal direction, and the first thickness may be less than or equal to the second thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.