Method of manufacturing a semiconductor device and a semiconductor device
US11393898B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 21, 2020 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Jul 21, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/832
Abstract
In a method of manufacturing a semiconductor device, a fin structure in which first semiconductor layers and second semiconductor layers are alternately stacked is formed, a sacrificial gate structure is formed over the fin structure, a source/drain region of the fin structure, which is not covered by the sacrificial gate structure, is etched, thereby forming a source/drain space, the first semiconductor layers are laterally etched through the source/drain space, and a source/drain epitaxial layer is formed in the source/drain space. An inner spacer made of a dielectric material is formed on an end of each of the etched first semiconductor layers and at least one of the spacer has width changes along vertical direction of device. At least one of the first semiconductor layers has a composition different from another of the first semiconductor layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.