High-density dual-embedded microstrip interconnects
US11395402B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 25, 2018 |
| Grant date | Jul 19, 2022 |
| Priority date | — |
| Expiry date | Nov 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2201/10545
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In accordance with embodiments disclosed herein, there is provided a high-density dual-embedded-microstrip interconnect. An interconnect includes a reference layer and a dielectric disposed on the reference layer. The interconnect further includes a pair of conductors including a first conductor and a second conductor that are in an edge-facing orientation. The interconnect further includes a third conductor. The pair of conductors may be disposed within the dielectric and the third conductor may be disposed on the dielectric above the pair of conductors. The pair of conductors may be disposed on the dielectric and the third conductor may be disposed within the dielectric below the pair of conductors. First noise received by the third conductor from the first conductor and second noise received by the third conductor from the second conductor at least partially cancel out.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.